In general, a high-voltage lateral double diffused MOS transistor (LDMOS) is one type of power device that is widely used for control, logic, or power switches. The LDMOS transistor should have a high breakdown voltage that can be sustained even when a high voltage is applied to the LDMOS. The LDMOS transistor should also have a low on-resistance so that a high switching characteristic can be maintained.
FIG. 1 is a cross-sectional view illustrating a conventional LDMOS transistor. As shown in FIG. 1, a high-concentration n-type (n+) burying layer 12 is formed deep in a p-type substrate 10, and a low-concentration n-type (n−) epitaxial layer 14 (or an n− well) having a predetermined thickness is grown on the n+ burying layer 12. A gate electrode 18 containing gate insulating layers 16a and 16b is formed in a predetermined portion on the n− epitaxial layer 14. The first gate insulating layer 16a has a thin film and the second gate insulating layer 16b has a thick film. A spacer 20 is formed by a well-known method on both sidewalls of the gate electrode 18.
A p body region 24 is formed under and to one side of the gate electrode 18. An n+ source region 26 and a high concentration p-type (p+) contact region 28 are formed in the p body region 24. In this transistor, the p body region 24 is formed with a relatively high concentration so that punch-through can be prevented from occurring in the LDMOS transistor.
The transistor illustrated in FIG. 1 also contains an n− channel stop region 30 with a predetermined junction depth under and on one side of the gate electrode 18. This transistor also contains an n+ drain region 32 that is formed in the n− channel stop region 30. The n− channel stop region 30 is formed in the LDMOS transistor as a stopper for intercepting the extension of the channel. The n− channel stop region 30 has a concentration higher than the n− epitaxial layer 14, thereby reducing the on-resistance. At the same time, the n− channel stop region 30 has a relatively low concentration, thereby exhibiting a high breakdown voltage. The transistor illustrated in FIG. 1 also contains a gate, a source, and a drain that are connected to the gate electrode 18, the source region 26 and the p+ contact region 28, and the drain region 32, respectively.
The conventional LDMOS transistor illustrated in FIG. 1 has a profile in which a body concentration of the channel region C is inclined. Further, the p body region 24 (where a channel is formed) is formed with a relatively high concentration in consideration of punch-through. Meanwhile, the n− epitaxial layer 14 is formed with a low concentration in consideration of the breakdown voltage. As a result, the on-resistance of the channel region C cannot be accurately controlled, and since the n− epitaxial layer 14 has a low concentration, a low on-resistance is not easily obtained.